devcsr.h

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/*************************************************************************\
* Copyright (c) 2010 Brookhaven Science Associates, as Operator of
*     Brookhaven National Laboratory.
* Copyright (c) 2006 The University of Chicago,
*     as Operator of Argonne National Laboratory.
* Copyright (c) 2006 The Regents of the University of California,
*     as Operator of Los Alamos National Laboratory.
* Copyright (c) 2006 The Board of Trustees of the Leland Stanford Junior
*     University, as Operator of the Stanford Linear Accelerator Center.
* devLib2 is distributed subject to a Software License Agreement found
* in file LICENSE that is included with this distribution.
\*************************************************************************/
/*
 * Author: Michael Davidsaver <mdavidsaver@gmail.com>
 */

#ifndef DEVLIBCSR_H
#define DEVLIBCSR_H 1

#include <epicsVersion.h>

#if EPICS_VERSION==3 && EPICS_REVISION==14 && EPICS_MODIFICATION<10
#  include "devLibVME.h"
#else
#  include "devLib.h"
#endif

#include <epicsTypes.h>
#include "epicsMMIO.h"
#include "vmedefs.h"

#include <shareLib.h>

#ifdef __cplusplus
extern "C" {

#  ifndef INLINE
#    define INLINE inline
#  endif
#endif

#define DEVLIBVME_MAJOR 1 
#define DEVLIBVME_MINOR 0 
struct VMECSRID {
        epicsUInt32 vendor,board,revision;
};

#define VMECSR_END {0,0,0}

#define VMECSRANY 0xFfffFfff

#define VMECSRSLOTMAX ((1<<5)-1)

epicsShareFunc
volatile unsigned char* devCSRProbeSlot(int slot);

epicsShareFunc
volatile unsigned char* devCSRTestSlot(
        const struct VMECSRID* devs,
        int slot,
        struct VMECSRID* info
);

#define CSRSlotBase(slot) ( (slot)<<19 )

#define CSRADER(addr,mod) ( ((addr)&0xFfffFf00) | ( ((mod)&0x3f)<<2 ) )

/* Read/Write CR for standard sizes
 */

#define CSRRead8(addr) ioread8(addr)

#define CSRRead16(addr) ( CSRRead8(addr)<<8 | CSRRead8(addr+4) )

#define CSRRead24(addr) ( CSRRead16(addr)<<8 | CSRRead8(addr+8) )

#define CSRRead32(addr) ( CSRRead24(addr)<<8 | CSRRead8(addr+12) )

#define CSRWrite8(addr,val) iowrite8(addr, val)

#define CSRWrite16(addr,val) \
do{ CSRWrite8(addr,(val&0xff00)>>8); CSRWrite8(addr+4,val&0xff); }while(0)

#define CSRWrite24(addr,val) \
do{ CSRWrite16(addr,(val&0xffff00)>>8); CSRWrite8(addr+8,val&0xff); }while(0)

#define CSRWrite32(addr,val) \
do{ CSRWrite24(addr,(val&0xffffff00)>>8); CSRWrite8(addr+12,val&0xff); }while(0)

/*
 * Utility functions
 */

epicsShareExtern void vmecsrprint(int N,int verb);

epicsShareExtern void vmecsrdump(int verb);

/**************************************************************************************************/
/*  CR/CSR Configuration ROM (CR) Register Definitions                                            */
/**************************************************************************************************/

/* VME64 required CR registers */

#define  CR_ROM_CHECKSUM           0x0003 
#define  CR_ROM_LENGTH             0x0007 
#define  CR_DATA_ACCESS_WIDTH      0x0013 
#define  CSR_DATA_ACCESS_WIDTH     0x0017 
#define  CR_SPACE_ID               0x001B 
#define  CR_ASCII_C                0x001F 
#define  CR_ASCII_R                0x0023 
#define  CR_IEEE_OUI               0x0027 
#define  CR_IEEE_OUI_BYTES                     3   
#define  CR_BOARD_ID               0x0033 
#define  CR_BOARD_ID_BYTES                     4   
#define  CR_REVISION_ID            0x0043 
#define  CR_REVISION_ID_BYTES                  4   
#define  CR_ASCII_STRING           0x0053 
#define  CR_PROGRAM_ID             0x007F 
/* VME64x required CR registers */

#define  CR_BEG_UCR                0x0083 
#define  CR_END_UCR                0x008F 
#define  CR_BEG_UCSR_BYTES                     3   
#define  CR_BEG_CRAM               0x009B 
#define  CR_END_CRAM               0x00A7 
#define  CR_BEG_UCSR               0x00B3 
#define  CR_END_UCSR               0x00BF 
#define  CR_BEG_SN                 0x00CB 
#define  CR_END_SN                 0x00DF 
#define  CR_SLAVE_CHAR             0x00E3 
#define  CR_UD_SLAVE_CHAR          0x00E7 
#define  CR_MASTER_CHAR            0x00EB 
#define  CR_UD_MASTER_CHAR         0x00EF 
#define  CR_IRQ_HANDLER_CAP        0x00F3 
#define  CR_IRQ_CAP                0x00F7 
#define  CR_CRAM_WIDTH             0x00FF 
#define  CR_FN_DAWPR(N)  ( 0x0103 + (N)*0x04 ) /* N = 0 -> 7 */

#define  CR_DAWPR_BYTES                        1   /* Number of bytes in a DAWPR register         */

#define  CR_FN_AMCAP(N)  ( 0x0123 + (N)*0x20 ) /* N = 0 -> 7 */

#define  CR_AMCAP_BYTES                        8   /* Number of bytes in an AMCAP register        */

#define  CR_FN_XAMCAP(N) ( 0x0223 + (N)*0x80 ) /* N = 0 -> 7 */

#define  CR_XAMCAP_BYTES                      32   /* Number of bytes in an XAMCAP register       */

#define  CR_FN_ADEM(N)   ( 0x0623 + (N)*0x10 ) /* N = 0 -> 7 */

#define  CR_ADEM_BYTES                         4   /* Number of bytes in an ADEM register         */

#define  CR_MASTER_DAWPR           0x06AF 
#define  CR_MASTER_AMCAP           0x06B3 
#define  CR_MASTER_XAMCAP          0x06D3 
/*---------------------
 * Size (in total bytes) of CR space
 */
#define  CR_SIZE                          0x0750   
#define  CR_BYTES                   (CR_SIZE>>2)   
/**************************************************************************************************/
/*  CR/CSR Control and Status Register (CSR) Offsets                                              */
/**************************************************************************************************/

/* VME64 required CSR registers */

#define  CSR_BAR                0x7ffff 
#define  CSR_BIT_SET            0x7fffb 
#define  CSR_BIT_CLEAR          0x7fff7 
/* VME64x required CSR registers */

#define  CSR_CRAM_OWNER         0x7fff3 
#define  CSR_UD_BIT_SET         0x7ffef 
#define  CSR_UD_BIT_CLEAR       0x7ffeb 
#define  CSR_FN_ADER(N) (0x7ff63 + (N)*0x10) /* N = 0 -> 7 */

#define  CSR_ADER_BYTES                     4   /* Number of bytes in an ADER register            */

/*---------------------
 * Bit offset definitions for the Bit Set Status Register
 */
#define  CSR_BITSET_RESET_MODE           0x80   
#define  CSR_BITSET_SYSFAIL_ENA          0x40   
#define  CSR_BITSET_MODULE_FAIL          0x20   
#define  CSR_BITSET_MODULE_ENA           0x10   
#define  CSR_BITSET_BERR                 0x08   
#define  CSR_BITSET_CRAM_OWNED           0x04   
/* Common things to set in CSR
 */

INLINE
void
CSRSetBase(volatile void* base, epicsUInt8 N, epicsUInt32 addr, epicsUInt8 amod)
{
  volatile char* ptr=(volatile char*)base;
  if (N>7) return;
  CSRWrite32((ptr) + CSR_FN_ADER(N), CSRADER(addr,amod) );
}

#ifdef __cplusplus
} /* extern "C" */
#endif

#endif /* DEVLIBCSR_H */