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| #define | DEVLIBVME_MAJOR 1 |
| | API major version. More...
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| #define | DEVLIBVME_MINOR 0 |
| | API minor version. More...
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| #define | VMECSR_END {0,0,0} |
| | Must be the last entry in a device list. More...
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| #define | VMECSRANY 0xFfffFfff |
| | Match any value. May be used in any field of VMECSRID. More...
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| #define | VMECSRSLOTMAX ((1<<5)-1) |
| | The highest slot number. More...
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| #define | CSRSlotBase(slot) ( (slot)<<19 ) |
| | Derives the CSR space base address for a slot. More...
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| #define | CSRADER(addr, mod) ( ((addr)&0xFfffFf00) | ( ((mod)&0x3f)<<2 ) ) |
| | Computes values for the VME64x address decode registers (ADER). More...
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| #define | CSRRead8(addr) ioread8(addr) |
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| #define | CSRRead16(addr) ( CSRRead8(addr)<<8 | CSRRead8(addr+4) ) |
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| #define | CSRRead24(addr) ( CSRRead16(addr)<<8 | CSRRead8(addr+8) ) |
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| #define | CSRRead32(addr) ( CSRRead24(addr)<<8 | CSRRead8(addr+12) ) |
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| #define | CSRWrite8(addr, val) iowrite8(addr, val) |
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| #define | CSRWrite16(addr, val) do{ CSRWrite8(addr,(val&0xff00)>>8); CSRWrite8(addr+4,val&0xff); }while(0) |
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| #define | CSRWrite24(addr, val) do{ CSRWrite16(addr,(val&0xffff00)>>8); CSRWrite8(addr+8,val&0xff); }while(0) |
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| #define | CSRWrite32(addr, val) do{ CSRWrite24(addr,(val&0xffffff00)>>8); CSRWrite8(addr+12,val&0xff); }while(0) |
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| #define | CR_ROM_CHECKSUM 0x0003 |
| | 8-bit checksum of Configuration ROM space More...
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| #define | CR_ROM_LENGTH 0x0007 |
| | Number of bytes in Configuration ROM to checksum. More...
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| #define | CR_DATA_ACCESS_WIDTH 0x0013 |
| | Configuration ROM area (CR) data access method. More...
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| #define | CSR_DATA_ACCESS_WIDTH 0x0017 |
| | Control/Status Reg area (CSR) data access method. More...
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| #define | CR_SPACE_ID 0x001B |
| | CR/CSR space ID (VME64, VME64X, etc). More...
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| #define | CR_ASCII_C 0x001F |
| | ASCII "C" (identifies this as CR space) More...
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| #define | CR_ASCII_R 0x0023 |
| | ASCII "R" (identifies this as CR space) More...
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| #define | CR_IEEE_OUI 0x0027 |
| | IEEE Organizationally Unique Identifier (OUI) More...
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| #define | CR_IEEE_OUI_BYTES 3 |
| | Number of bytes in manufacturer's OUI. More...
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| #define | CR_BOARD_ID 0x0033 |
| | Manufacturer's board ID. More...
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| #define | CR_BOARD_ID_BYTES 4 |
| | Number of bytes in manufacturer's OUI. More...
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| #define | CR_REVISION_ID 0x0043 |
| | Manufacturer's board revision ID. More...
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| #define | CR_REVISION_ID_BYTES 4 |
| | Number of bytes in board revision ID. More...
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| #define | CR_ASCII_STRING 0x0053 |
| | Offset to ASCII string (manufacturer-specific) More...
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| #define | CR_PROGRAM_ID 0x007F |
| | Program ID code for CR space. More...
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| #define | CR_BEG_UCR 0x0083 |
| | Offset to start of manufacturer-defined CR space. More...
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| #define | CR_END_UCR 0x008F |
| | Offset to end of manufacturer-defined CR space. More...
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| #define | CR_BEG_UCSR_BYTES 3 |
| | Number of bytes in User CSR starting offset. More...
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| #define | CR_BEG_CRAM 0x009B |
| | Offset to start of Configuration RAM (CRAM) space. More...
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| #define | CR_END_CRAM 0x00A7 |
| | Offset to end of Configuration RAM (CRAM) space. More...
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| #define | CR_BEG_UCSR 0x00B3 |
| | Offset to start of manufacturer-defined CSR space. More...
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| #define | CR_END_UCSR 0x00BF |
| | Offset to end of manufacturer-defined CSR space. More...
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| #define | CR_BEG_SN 0x00CB |
| | Offset to beginning of board serial number. More...
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| #define | CR_END_SN 0x00DF |
| | Offset to end of board serial number. More...
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| #define | CR_SLAVE_CHAR 0x00E3 |
| | Board's slave-mode characteristics. More...
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| #define | CR_UD_SLAVE_CHAR 0x00E7 |
| | Manufacturer-defined slave-mode characteristics. More...
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| #define | CR_MASTER_CHAR 0x00EB |
| | Board's master-mode characteristics. More...
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| #define | CR_UD_MASTER_CHAR 0x00EF |
| | Manufacturer-defined master-mode characteristics. More...
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| #define | CR_IRQ_HANDLER_CAP 0x00F3 |
| | Interrupt levels board can respond to (handle) More...
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| #define | CR_IRQ_CAP 0x00F7 |
| | Interrupt levels board can assert. More...
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| #define | CR_CRAM_WIDTH 0x00FF |
| | Configuration RAM (CRAM) data access method) More...
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| #define | CR_FN_DAWPR(N) ( 0x0103 + (N)*0x04 ) /* N = 0 -> 7 */ |
| | Start of Data Access Width Parameter (DAWPR) regs. More...
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| #define | CR_DAWPR_BYTES 1 /* Number of bytes in a DAWPR register */ |
| |
| #define | CR_FN_AMCAP(N) ( 0x0123 + (N)*0x20 ) /* N = 0 -> 7 */ |
| | Start of Address Mode Capability (AMCAP) registers. More...
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| #define | CR_AMCAP_BYTES 8 /* Number of bytes in an AMCAP register */ |
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| #define | CR_FN_XAMCAP(N) ( 0x0223 + (N)*0x80 ) /* N = 0 -> 7 */ |
| | Start of Extended Address Mode Cap (XAMCAP) registers. More...
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| #define | CR_XAMCAP_BYTES 32 /* Number of bytes in an XAMCAP register */ |
| |
| #define | CR_FN_ADEM(N) ( 0x0623 + (N)*0x10 ) /* N = 0 -> 7 */ |
| | Start of Address Decoder Mask (ADEM) registers. More...
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| #define | CR_ADEM_BYTES 4 /* Number of bytes in an ADEM register */ |
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| #define | CR_MASTER_DAWPR 0x06AF |
| | Master Data Access Width Parameter. More...
|
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| #define | CR_MASTER_AMCAP 0x06B3 |
| | Master Address Mode Capabilities (8 entries) More...
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| #define | CR_MASTER_XAMCAP 0x06D3 |
| | Master Extended Address Mode Capabilities (8 entries) More...
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| #define | CR_SIZE 0x0750 |
| | Size of CR space (in total bytes) More...
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| #define | CR_BYTES (CR_SIZE>>2) |
| | Number of bytes in CR space. More...
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| #define | CSR_BAR 0x7ffff |
| | Base Address Register (MSB of our CR/CSR address) More...
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| #define | CSR_BIT_SET 0x7fffb |
| | Bit Set Register (writing a 1 sets the control bit) More...
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| #define | CSR_BIT_CLEAR 0x7fff7 |
| | Bit Clear Register (writing a 1 clears the control bit) More...
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| #define | CSR_CRAM_OWNER 0x7fff3 |
| | Configuration RAM Owner Register (0 = not owned) More...
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| #define | CSR_UD_BIT_SET 0x7ffef |
| | User-Defined Bit Set Register (for user-defined fns) More...
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| #define | CSR_UD_BIT_CLEAR 0x7ffeb |
| | User-Defined Bit Clear Register (for user-defined fns) More...
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| #define | CSR_FN_ADER(N) (0x7ff63 + (N)*0x10) /* N = 0 -> 7 */ |
| | Function N Address Decoder Compare Register (1st byte) More...
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| #define | CSR_ADER_BYTES 4 /* Number of bytes in an ADER register */ |
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| #define | CSR_BITSET_RESET_MODE 0x80 |
| | Module is in reset mode. More...
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| #define | CSR_BITSET_SYSFAIL_ENA 0x40 |
| | SYSFAIL driver is enabled. More...
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| #define | CSR_BITSET_MODULE_FAIL 0x20 |
| | Module has failed. More...
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| #define | CSR_BITSET_MODULE_ENA 0x10 |
| | Module is enabled. More...
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| #define | CSR_BITSET_BERR 0x08 |
| | Module has asserted a Bus Error. More...
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| #define | CSR_BITSET_CRAM_OWNED 0x04 |
| | CRAM is owned. More...
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