INLINE epicsUInt8	ioread8 (volatile void *addr)
	Read a single byte. More...

INLINE epicsUInt16	bswap16 (epicsUInt16 value)

#define	rbarr() do{}while(0)
	Explicit read memory barrier Prevents reordering of reads around it. More...

#define	wbarr() do{}while(0)
	Explicit write memory barrier Prevents reordering of writes around it. More...

#define	rwbarr() do{}while(0)
	Explicit read/write memory barrier Prevents reordering of reads or writes around it. More...

Detailed Description

Safe operations on I/O memory.

This files defines a set of macros for access to Memory Mapped I/O

They are named T_ioread# and T_iowrite# where # can be 8, 16, or 32. 'T' can either be 'le', 'be', or 'nat' (except ioread8 and iowrite8).

The macros defined use OS specific extensions (when available) to ensure the following.

Width. A 16 bit operation will not be broken into two 8 bit operations, or one half of a 32 bit operation.

Order. Writes to two different registers will not be reordered. This only applies to MMIO operations, not between MMIO and normal memory operations.

PCI access should use either 'le_' or 'be_' as determined by the device byte order.

VME access should always use 'nat_'. If the device byte order is little endian then an explicit swap is required.

Examples:

Big endian device:

PCI

be_iowrite16(base+off, 14);

var = be_ioread16(base+off);

VME

nat_iowrite16(base+off, 14);

var = nat_ioread16(base+off);

Little endian device

PCI

le_iowrite16(base+off, 14);

var = le_ioread16(base+off);

VME

nat_iowrite16(base+off, bswap16(14));

var = bswap16(nat_iowrite16(base+off));

This difference arises because VME bridges implement hardware byte swapping on little endian systems, while PCI bridges do not. Software accessing PCI devices must know if byte swapping is required. This conditional swap is implemented by the 'be_' and 'le_' macros.

This is a fundamental difference between PCI and VME.

Software accessing PCI must do conditional swapping.

Software accessing VME must not do conditional swapping.

Note: All read and write operations have an implicit read or write barrier.

Macro Definition Documentation

◆ rbarr

#define rbarr ( ) do{}while(0)

Explicit read memory barrier Prevents reordering of reads around it.

Definition at line 194 of file epicsMMIODef.h.

◆ rwbarr

#define rwbarr ( ) do{}while(0)

Explicit read/write memory barrier Prevents reordering of reads or writes around it.

Definition at line 202 of file epicsMMIODef.h.

◆ wbarr

#define wbarr ( ) do{}while(0)

Explicit write memory barrier Prevents reordering of writes around it.

Definition at line 198 of file epicsMMIODef.h.

Function Documentation

◆ bswap16()

INLINE epicsUInt16 bswap16 ( epicsUInt16 value )

Definition at line 94 of file epicsMMIODef.h.

◆ ioread8()

INLINE epicsUInt8 ioread8 ( volatile void * addr )

Read a single byte.

Definition at line 32 of file epicsMMIODef.h.